It is known that certain manufacturing processes such as ion implantation, plasma etching, and other charged beam processes may cause damage to workpieces, such as semiconductor wafers, and the devices and circuits formed therein. In particular, electrical charging is a well known problem which can occur during the plasma processing of semiconductor devices leading to the degradation of the device performance. Electrical charging can, for example, be a problem when there are large antennas of conducting material such as metal or polysilicon attached to a transistor gate that utilizes a very thin (e.g., less than 100 angstroms) gate oxide. These antennas serve to collect a relatively high level of electrical charge by virtue of their large area. This electrical charge may then be funneled down onto a transistor (or other device) leading to performance degradation or outright destruction of the device.
In an effort to measure and/or characterize the charging that occurs during plasma processing, circuits have been developed to measure the resulting voltage potential (or a current flow) between a charge collection area on the surface of the semiconductor device wafer and the substrate of the semiconductor wafer. Circuits, such as these, are typically provided within the semiconductor wafer. For example, U.S. Pat. No. 5,315,145 describes a charge monitoring device using an EEPROM device that functions as a high impedance voltage sensor and/or current sensor with a memory capability.
By way of example, FIGS. 1a-1c are schemetic cross-sectional views of three semiconductor wafers including different conventional charge monitoring devices. The semiconductor wafer includes a plurality of layers including a substrate 12 and an oxide layer 14. Each of the charge monitoring devices in FIGS. 1a, 1b and 1c includes an electrically programmable memory device having an Electrically Erasable Programmable Read Only Memory (EEPROM) transistor 16 for measuring and/or characterizing the charge that accumulates on a charge collection electrode (CCE) 18 (e.g., located on the surface of the wafer) during plasma processing.
A voltage sensor 10 is depicted in FIG. 1a. Voltage sensor 10 measures the positive potential between CCE 18 and substrate 12. Voltage sensor 10 includes EEPROM transistor 16 having a control electrode 20, a floating gate electrode 22, and source region 26 and drain regions 27. Control electrode 20 is connected to CCE 18. Floating electrode 22 located within oxide layer 14, includes a projection 24 that extends towards source region 26. Additionally, voltage sensor 10 includes a shunt diode 30 that is connected between CCE 18 and substrate 12. As depicted in FIG. 1a, diode 30 is connected to allow EEPROM transistor 16 to sense a positive potential between CCE 18 and substrate 12. If diode 30 is connected in the opposite direction between CCE 18 and substrate 12, as depicted by diode 30' in FIG. 1b, then voltage sensor 10' measures the negative potential between CCE 18 and substrate 12.
In other charge monitoring devices, diode 30 (or 30') are not required. However, the EEPROM transistor 16 in the resulting voltage sensor is affected by both positive and negative electrical charging during the process.
Furthermore, as depicted in FIG. 1 c, wherein diode 30 (or 30') is replaced by a resistor 32, EEPROM transistor 16 in voltage sensor 10" measures the voltage drop across resistor 32 as a result of the electrical charge accumulated on CCE 18 and the charge flux between CCE 18 and substrate 12. Thus, voltage sensor 10" is essentially a charge flux sensor, or current sensor.
For a workpiece, such as a semiconductor wafer, several charge monitoring devices (e.g., those depicted in FIGS. 1a-c) are typically provided to monitor the wafer during fabrication and processing. To perform the desired measurements using these devices, a threshold voltage (V.sub.t1) associated with EEPROM transistor 16 is programmed prior to exposing the wafer to a process, such as a plasma process. Programming is typically accomplished by probing the wafer and supplying a programming signal to EEPROM transistor 16 via CCE 18.
After the plasma process is completed, each EEPROM transistor 16 is again probed and a resulting threshold voltage (V.sub.t2) is measured. The measurement V.sub.t2 is typically accomplished by a parametric tester (not shown). This programming and measuring procedure is repeatable because each EEPROM transistor 16 is re- programmable.
Once V.sub.t1, and V.sub.t2 for a particular voltage sensor 10 are known, then the surface potential and charging is determined by using a calibration curve 35, as depicted in FIG. 2. Calibration curve 35 is a plot of threshold voltage V.sub.T versus a control gate voltage V.sub.G for an exemplary EEPROM transistor, where V.sub.T equals the difference in absolute magnitude between V.sub.t1 and V.sub.t2. Calibration curve 35 depicts the substantially linear relationship between V.sub.T and V.sub.G.
If V.sub.t2 is higher in absolute magnitude than V.sub.t1, then the right-hand side 36 of calibration curve 35 is used to determine V.sub.G based on V.sub.T. If V.sub.t2 is lower in absolute magnitude than V.sub.t1, then the left-hand side 38 of calibration curve 35 is used to determine V.sub.G based on V.sub.T. In either situation, V.sub.G represents the potential between CCE 18 and substrate 12. Further, if voltage sensor 10 includes a known resistance, such as resistor 32 in FIG. 1c, between CCE 18 and substrate 12, then the current that flowed through the resistor during plasma processing can be determined by applying Ohm's law (e.g., the current equals V.sub.G divided by the known resistance).
Charge monitoring devices, such as the prior art voltage and current sensors depicted in FIGS. 1a-c, are able to detect global wafer charging caused by non-uniformities in the plasma. The non-uniformities, if significant enough, can lead to macroscopic level charging of the wafer. However, prior art charge monitoring devices are less effective in measuring charging occurring at the local microscopic level due to the topology of the fabricated device structure. Microscopic level charging can occur in a uniform plasma and is often dependent upon the pattern of the exposed surface of the wafer. For example, charging due to "electron shading", caused by the physical structure of the device is difficult to measure with the prior art charge monitoring devices.